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NXP Semiconductors
Quadruple ESD transient voltage
suppressor
Product data sheet
BZA900A-series
APPLICATION INFORMATION
Typical common anode application
A quadruple transient suppressor in a SOT665 package makes it possible to protect four separate lines using only one
package. A simplified example is shown in Fig.7.
handbook, full pagewidth
A
keyboard,
terminal,
printer,
etc.
I/O
B
C
D
FUNCTIONAL
DECODER
BZA900A
GND
MGW316
Fig.7 Computer interface protection.
Device placement and printed-circuit board layout
Circuit board layout is of extreme importance in the suppression of transients. The clamping voltage of the BZA900A is
determined by the peak transient current and the rate of rise of that current (di/dt). Since parasitic inductances can further
add to the clamping voltage (V = L di/dt) the series conductor lengths on the printed-circuit board should be kept to a
minimum. This includes the lead length of the suppression element.
In addition to minimizing conductor length the following printed-circuit board layout guidelines are recommended:
1. Place the suppression element close to the input terminals or connectors
2. Keep parallel signal paths to a minimum
3. Avoid running protection conductors in parallel with unprotected conductors
4. Minimize all printed-circuit board loop areas including power and ground loops
5. Minimize the length of the transient return path to ground
6. Avoid using shared transient return paths to a common ground point.
2001 Sep 03
6
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